At present in the field of global semiconductor industry, industry insiders think 2.5 D chip product cost of advanced packaging technology, the future will be as related products production and more and more low, but this assumption may ignore the technology itself and manufacturers operating management faces many problems and difficulties, may not be so easy to predict future price movements in the emerging packaging technology products.

Semiconductor Engineering web site reported, with 2.5 D advanced packaging technology, from the most common voice chip manufacturer and equipment supplier, that is used to link all kinds of grain in packaging technology of a mediation layer (interposer) cost is too high, or a mask as cost too high to to 14 or 16 nano process, the development of complex plane type (planar) system of single chip (SoC); Or a Silicon oxygen insulation gold as half a transistor components (FD - SOI) than 28 nm blank Silicon wafer (Bulk Silicon) is expensive, and so on.

But the idea might be a bit misleading, even more complex SoC has certain degree of increase production cost, but also has some cost savings, some can even save costs substantially. As the second generation of high frequency width memory (HBM2) the launch of its regardless of price, efficiency and power than DRAM, appearance also significantly smaller size.

, SK Hynix (SK Hynix) technology, senior marketing manager Kevin Tran, points out that four stack chips, 2.5 D packaging technology HBM2 memory is roughly equivalent to DDR4 particles, more important is to increase the bandwidth, installation dimensions are smaller, more energy saving and low delay time is more advantage. As such emerging storage caliber is produced, is expected to see the similar past DRAM market prices downward trend.

However, whether the HBM memory really expected to see prices decline trend in the future, there may still be worth exploring. First of all, the current has been difficult to analogy to do different storage technology specifications, in HBM storage technology may adopt different architecture design cases, it is not so easily to compare different storage technology specifications.

Second, the cost of change the topic is not so simple, because this is not only the memory or the cost of a mediation layer, more important is to see how to configure the cost of production in each chip manufacturer, owned by different departments. Now chip maker, has less investment funds in learn more about how should adjust the basic business processes, but more focus on getting engineers throughout the design process, also has such as software, hardware before and after the end of technical knowledge.

Therefore 2.5 D and fan out from the industry type (fan - outs) packaging technology import, the smaller the chip has better yield obviously, even if the combined cost is higher, so this is why the spirit (Xilinx) and Altera start developing 2.5 D chip.

If the design for power consumption and heat dissipation problem, can spend less costs, is used to design, develop and manufacture the overall cost of this kind of 2.5 D chip, should be expected to continue to fall.

But even for the whole and in the past few years the global semiconductor industry, nor such consolidation above 2.5 D packaging technology as a decline in the cost of whole chip development, because of, in fact, if you want to integrate technology and engineering resources, there have been no small difficulty, will do the business side more difficult integration.

Because often inside the large system operators, business process more complicated than developing products, adjusting speed, often also is slower than the technical side. So if you can improve the field of perhaps more help to really improve cost expenditure scale and structure.