SemiconductorEngineering web site reported, miniature cost increased uncertainty for global supply chain into a stock. Resource security giant, is expected to be sustained progress until at least 7 nm.

Whether to take the more subtle process, must inspect EUV, multiple beam (such as Multi - e - beam lithography technology and directional self-assembly technology (Directedself - assembly), quantum effects, new materials and new transistor architecture development.

Now tended to advance the miniature market makers believe, should not have 10 nanometers, and as the market is most worried about chip factory prepare new node takes too long, so skip such as 20 nanometers half node, the situation will appear in even 10 nanometers.

Arteris executive CharlieJanac said that 10 nanometers progress too fast, causing makers worry can't recycle, and the market also wait for 5 nm, because its investment cost will be considerable. Therefore, seven nanometers will maintain a period of time, including SubramaniKengeri GlobalFoundries vice President also think that next time to 7 nm and lasts for a period of time.

For the server, the GPU, mobile phone and the field programmable gate array (FPGA) chip manufacturers design, past will actively promote the most advanced process, but the rest will no longer follow the fab, preferring the including plane type completely empty of insulating layer overlying the silicon (SOI) PlanarFD - type, 2.5 D and fan out (fan - out) and integration of 3 D technology.

MikeGianfagna eSilicon vice President pointed out that technology will overlap, although 2.5 D let technology options increase, but the yield is still uncertainty.

Now let operators willing to put into research and development of new motivation has been forming, although mobile phones will continue to drive the system single chip (SoC) market growth, but its growth rate has slowed, once the market mature, will make the product appear pricing pressure. Evolution of computer (Cadence) marketing director, points out that the cost is the main considerations, and the industry has begun to think from lower the product cost, especially to reduce the chip cost.

Traditionally, after the advent of each new generation process is used in great quantities in the market must be able to appear to make fabs continue to invest in new process, but after 28 nm, due to various process are different, on behalf of the tool, IP and equipment need to be customized. Once in nano after 16/14, uncertainty factors include EUV and whether the electron beam lithography, etc., so more companies reluctant to invest in a process.

, on the other hand, as the technology option, the manufacturer is no longer blindly toward the new process. Such as samsung electronics (SamsungElectronics), STMicroelectronics (STMicroelectronics), France CEA - Leti electronic information technology laboratory and GlobalFoundries support FD - SOI technology.

Comments that FD SOI after 16/14 nano - whether still competitive is still in doubt, because why lithography is the key, as for GlobalFoundries tended to 10 nm plane FD - SOI, hope to omit double exposure and FinFET need.

But eSilicon is conservative attitude, and points out that the FD - FD SOI shipments amount and blueprint - SOI is not yet clear, even if it is good to have many options market, but the FD - SOI did not replace FinFET. The market, however, there are other hedging strategies, such as using 2.5 D and type fan out (fan - out), including TSMC launch InFo has obtained the stability.

In addition, sea (Hisilicon), ase and Marvell (Marvell) has developed the commercial practices 2.5 D chip, huawei, IBM and superfine (AMD) is responsible for sales. Arteris thought, therefore, the market will eventually go in 3 d, let the assembly house status is more important.

Even so, investors believe once the problem solved, cost will begin to decrease, GlobalFoundries think, 2.5 D can application market has 3 kinds, including the large grain broken down into small parts to improve yield, try to encapsulate the chip or module function maximization and the chip segmentation become independent parts and are connected by a mediation layer, the current marvell, ase and Tezzaron second technique is adopted.

Commentary pointed out that surround type gate FET, nanowires, 2.5 D, field-effect transistors full3D - IC, horizon three-dimensional integrated circuits (Monolithic3D - IC) or different technologies, such as fan out main fabs are ready to adopt, including samsung and GlobalFoundries the FD - SOI, sealing testing companies with a focus on the most advanced testing technology.

With the study diligence manufacturers, the market will naturally appear a new generation of technology, industry think which can reduce cost, is the key factor in decision could win.