1, BGA (ball grid array)

The spherical contact display, SMT type one of encapsulation. In the printing substrate on the back of the display mode to produce spherical convex point to replace pin, in the front of the printing substrate assembly LSI chips, then by moulding resin or potting method for sealing. Also known as the convex point display carrier (PAC). Pin can be more than 200, is one of the LSI with more pin encapsulation. Encapsulation body also can do better than QFP (four side pin flat pack). Pin, for example, center distance of 1.5 mm 360 pin BGA is only 31 mm square; And pin center distance of 0.5 mm 304 pin QFP is 40 mm square. And BGA don't have to worry about QFP pin deformation problem. The package was developed by Motorola companies in the United States, first of all be used in devices such as portable phone, in the future in the United States is likely to spread in the personal computer. Initially, BGA pin (convex point) of the center distance of 1.5 mm, pin number is 225. Now there are some manufacturer of LSI is developing 500 pin BGA. BGA problem after reflow soldering appearance inspection. It is unclear whether the appearance of the effective inspection method. Some think that due to large welding of center distance, connection can be regarded as a stable, only through a function to deal with. Motorola companies in the United States call with sealed moulded resin encapsulation OMPAC, and called the potting method sealed packaging GPAC (see OMPAC and GPAC).

2, BQFP (quad flat package with bumper)

With the four side of the pin cushion flat pack. One of QFP encapsulation, set in the four corners of the encapsulated ontology protrusions (cushion) in order to prevent the bending deformation occurred in the process of transporting pin. The semiconductor manufacturer mainly in microprocessor and ASIC circuit adopts the encapsulation. Pin center distance of 0.635 mm, pin number from 84 to 196 (see QFP).

3, touch welding PGA (Butt to be pin grid array)

SMT type of PGA nickname (see surface-mount PGA).

4, C - (Ceramic)

Mark said ceramic package. For example, CDIP represents ceramic DIP. In practice, however, is often used.

5, Cerdip

With glass sealed ceramic dual-in-line package, for ECL RAM, DSP (digital signal processor), and other circuit. With a glass window Cerdip type used for ultraviolet erasing an EPROM and internal microcomputer with EPROM circuit, etc. Pin center distance of 2.54 mm, pin number from 8 to 42. In Japan, the packaging is expressed as DIP - G glass seal (G).

6, Cerquad type surface-mount package, one of which is under the seal of the ceramic QFP, encapsulates DSP logic LSI circuit, etc. With a window Cerquad encapsulates an EPROM circuit. Good heat resistance than plastic QFP, under the condition of natural air cooling can allow 1.5 ~ 2 w power. But the packaging cost is higher than plastic QFP 3 ~ 5 times. Pin center distance is 1.27 mm, 0.8 mm and 0.65 mm, 0.5 mm and 0.4 mm, and other specifications. Pin number from 32 to 368.

7, CLCC (ceramic leaded chip carrier)

With pin ceramic chip carrier, SMT type packaging, one of the pins from the encapsulation of four sides, a crowd. With a window is used to encapsulate ultraviolet erasing an EPROM and microcomputer with EPROM circuit etc. The packaging is also known as QFJ, QFJ - G (see QFJ).

8, COB (chip on board)

Board chip packaging, is one of the bare chip SMT technology, on printed circuit boards, semiconductor chips handover pasted on the chip and the electrical connection in the substrate with suture method, lead the electrical connection in the chip and the substrate with suture method, lead and resin covered in order to ensure reliability. Although the COB is the simplest bare chip SMT technology, but it is much less than the TAB and the packing density slice of welding technology.

9, the DFP (dual flat package)

Bilateral foot flat pack. Is the SOP nickname (see the SOP). Once there is the France has now basically don't have to.

10, DIC (dual - line in ceramic package)

Ceramic DIP (including glass seal) nickname (DIP).

11, DIL (dual the in - line)

DIP the nickname (DIP). European semiconductor manufacturers use this name.

12, DIP (dual the in - line package)

Dual-in-line package. Cartridge type packaging, one of the pins from the wrap on both sides of, packaging material, which has two kinds of plastic and ceramic. DIP is the most popular type instrumentation encapsulation, applications include standard logic IC, memory LSI, microcomputer circuit, etc. Pin center distance of 2.54 mm, pin number from 6 to 64. Encapsulation width usually is 15.2 mm. Some encapsulate width 7.52 mm and 7.52 mm respectively called slim and skinny DIP DIP (DIP) narrow size. But in most cases is not distinction, simply referred to as a DIP. In addition, with low melting point glass sealed ceramic DIP also called cerdip (see cerdip).

13, DSO (dual small out - lint)

Bilateral pin small outline package. SOP's nickname (see the SOP). Part of the semiconductor manufacturer use this name.

14, DICP (dual tape carrier package)

Bilateral pin load encapsulation. One of the TCP (with packaging). Pin production carried and from the wrap on both sides of the insulation. Due to the use of "TAB (with automatic welding) technique, encapsulation shape is very thin. Often used for liquid crystal display driver LSI, but mostly on products. In addition, 0.5 mm thick shape memory LSI book packaging are under development. In Japan, according to the EIAJ electronic machinery industry (Japan) standards, named DICP DTP.

15, DIP (dual tape carrier package)

Same as above. Japan will electronic machinery industry standard of DTCP naming (see DTCP).

16, FP (flat package)

Flat pack. One of the SMT type packaging. QFP or SOP (see) QFP and SOP's nickname. Part of the semiconductor manufacturer use this name.

17, flip chip

Chip welding. One of bare chip packaging technology, the LSI chip electrode area is made of metal protruding points, and then the metal protruding point with the printing substrate electrode area of pressure welding connection. Encapsulates the occupied area is basically the same as the chip size. Is that all the packaging technology in one of the smallest, the thinnest.

But if the thermal expansion coefficient of substrate and LSI chip is different, will react in the joint, which affect the reliability of the connection. So must reinforce the LSI chips, with resin to thermal expansion coefficient and using essentially the same substrate material.

18, fQFP (fine pitch quad flat package)

Traditional operas of QFP foot center. Usually guide foot center distance is less than 0.65 mm of QFP (see QFP). Part of the guide conductor manufacturers use this name.

19, the CPAC (globe top pad array carrier)

Motorola companies in the United States of BGA nickname (BGA).

20, CQFP (quad fiat package with guard ring)

The four side of the belt protection ring pin flat pack. Plastic one of QFP, pin protection ring masking with resin, in order to prevent the bending deformation. Assemble at the LSI before printing substrate, cut off from the guard ring pin and make it become a sea gull wing shape (L). The encapsulation of Motorola company in the United States has batch production. Pin center distance of 0.5 mm, what is the maximum number of pins in around 208.

21, H - (with heat sink)

Said mark with the radiator. For example, HSOP means with the SOP of radiator.

22, the pin grid array (surface mount type)

SMT type PGA. Usually PGA for instrumentation encapsulation, pin is about 3.4 mm long. Surface-mount PGA in encapsulation type bottom has display of the pins, the length from 1.5 mm to 2.0 mm. SMT printing substrate is used to touch welding method, therefore, also known as touch welding PGA. Because the pin center distance is only 1.27 mm, is smaller than cartridge type PGA half, not very big, so encapsulation ontology can be crafted and pin number is more than the cartridge type (250 ~ 528), is for the use of large scale logic LSI encapsulation. Encapsulation of the substrate has a multilayer ceramic substrate epoxy resin and glass printing base. With multilayer ceramic substrate encapsulation has practical application.

23, JLCC (J - leaded chip carrier)

J shaped pin chip carrier. Refers to the window with CLCC and ceramic QFJ nickname with window (see CLCC and QFJ). Some manufacturers use the name of the semiconductor.

24, LCC (Leadless chip carrier)

No pin chip carrier. Refers to the four sides of the ceramic substrate electrode contact without pin but SMT type encapsulation. Is high speed and high frequency IC encapsulation, also known as ceramic QFN or QFN - C (see QFN).

25, the LGA (land grid array)

Contact display packaging. Array in the bottom is what is state of the electrode contact encapsulation. Plug the socket assembly. Already practical have 227 contact center distance (1.27 mm) and 447 contact center distance (2.54 mm) of the LGA ceramic, applied to high-speed LSI logic circuit. The LGA compared with QFP, to accommodate with smaller package more input/output pin. In addition, because of the small lead impedance, is very suitable for high speed LSI. But because the socket production complex, high cost, now basically is not how to use. Is expected in the future the demand will increase.

26, LOC (lead on chip)

Chip fuses encapsulation. LSI packaging technology, one of the front end of the lead frame in a structure above the chip, chip near the center of the convex solder joints, sewn up with lead to electrical connections. And used to decorate the lead frame in the chip, compared to the structure of the near side of the same size in encapsulation hold about chip up to 1 mm in width.

27, LQFP (low profile quad flat package)

QFP thin. Refers to encapsulate the ontology of QFP thickness of 1.4 mm, is Japan's electronic machinery industry will be formulated according to the new QFP specifications used the name of the shape.

28, L - QUAD

One of the ceramic QFP. Packaging substrates with aluminum nitride, the thermal conductivity 7 ~ 8 times higher than the alumina and has good heat resistance. Encapsulated in the framework of alumina, chip seal with potting method, thus inhibiting the costs. Is a kind of packaging for the logic of the development of LSI, under the condition of natural air cooling can allow the power of the W3. Has developed 208 pin center distance (0.5 mm) and 160 pin center distance (0.65 mm) of LSI logic with encapsulation, and put into mass production in October 1993.

29, MCM (multi chip module)

Chip components. Semiconductor bare chip assembly blocks on a wiring substrate of a kind of encapsulation. According to the substrate material can be divided into MCM -l, MCM - C and MCM -d three categories. MCM - L is used usually multilayer printed substrate glass epoxy resin components. Wiring density is not very high, the cost is low. MCM - C is the formation of multilayer wiring, with thick film technology in ceramic (alumina ceramic or glass) as the base plate component, and the use of multilayer ceramic substrate thick film hybrid IC similar. There was no significant difference. Wiring density higher than that of MCM - L. MCM -d is form multilayer wiring with membrane technology, ceramic (alumina and aluminum nitride) or Si, Al component as the base plate. Wiring plot is the highest in the three components, but the cost is high.

30, MFP (mini flat package)

Small flat pack. Plastic SOP or SSOP nickname (see the SOP and SSOP). Some manufacturers use the name of the semiconductor.

31, MQFP (metric quad flat package)

According to JEDEC (united electronics commission) standard of QFP a classification. Guide foot center distance of 0.65 mm thickness from 3.8 mm to 3.8 mm, ontology standard QFP (see QFP).

32, the MQUAD (metal quad)

Olin companies in the United States the development of a QFP encapsulation. Substrate with block adopts aluminum, with adhesive sealing. Under the condition of natural air cooling can allow the power of 2.5 W to 2.8 W. Japan xinguang electric industrial company charter in 1993 to start producing.

33, MSP (mini square package)

QFI nickname (see QFI), at the beginning of the development of many known as MSP. QFI is the name of the Japanese electronic machinery industry will regulations.

34, OPMAC (over molded pad array carrier)

Molding resin sealing convex point display carrier. Is used for the molding resin sealing BGA American Motorola company name (BGA).

35, P - (plastic)

The signs of the said plastic package. Such as plastic DIP PDIP said.

36, PAC (pad array carrier)

Convex point display carrier, BGA nickname (BGA).

37, PCLP (printed circuit board, leadless package)

Printed circuit board leadless package. Japan's Fujitsu to plastic QFN (LCC) plastic using the name of the (see QFN). Pin center distance is 0.55 mm and 0.4 mm two specifications. Is currently under development.

38, PFPF (plastic flat package)

Plastic flat pack. Plastic QFP nickname (see QFP). Use the name of the part of the LSI manufacturer.

39, PGA (pin grid array)

Display pin encapsulation. Cartridge type packaging, one of the bottom of the vertical pin is displayed. Encapsulation base material basically all use multilayer ceramic substrate in has not specifically expressed under the condition of material name, mostly ceramic PGA, used for high speed large scale logic LSI circuit. The high cost. Pin center distance of 2.54 mm, usually around the pin number from 64 to 64. In order to to reduce cost, packaging printing substrate instead of glass epoxy resin base material available. There are 64 ~ 256 pin plastic PGA. In addition, there is a pin center distance of 1.27 mm short pin type surface-mount PGA (touch welding PGA). (see surface-mount PGA).