Keywords: Intel
Last week Intel IDF's annual developers information technology summit held in 2016, chip giant Intel unveiled a lot of information about the current and future technology process technology, Intel had these things rarely mentioned, or as little as possible. So, Intel mentioned the conference about the details?
The second generation of 14 nano technology
Intel's most talked about topic is based on the manufacturing technology of "Derivative technology (Derivative Technologies)". The so-called derivative technology, according to Intel's explanation is "to improve performance, and function extension are becoming more common" technology. Therefore, based on Intel released the first derivative of technology: "14 +", you can also call it "14 nm +" or the second generation of 14 nanotechnology.
Intel said the "derivative" technology under the condition of the transistor and metal laminated, can at least get about 12% of the processor performance improvement.
Obviously, more perfect 14 nm process will take the lead in using the second generation to Intel's upcoming Kaby Lake micro architecture seventh generation core processors. If no accident, 14 nano server processors, released in 2017 will also be based on "14 nm +" process.
10 nanometers in three same wave products
Intel said, the future release 10 nanometers process, will be based on derivative iteration update technology points three times, respectively: "10", "10 +" and "10 + +", support a variety of the most leading products.
This means that, in the second half of 2017 released 10 nanotechnology is only the first generation product, then there is the continuation of the two generations, mainly with the improvement of chip underlying architecture and related process technology improvements, and for the proper performance enhancements.
Intel claims to notice density advantages rather than the crush
Intel said a lot about want to manufacturing technology competition outstanding, especially the chip unit intensive transistor density. In Intel's point of view, on a fixed chip area, able to plug into the more transistors, means it has more features and capabilities, rather than the pursuit of a new generation of technology process.
Interestingly, Intel also satirize the TSMC and samsung semiconductor industry competitors, points out that the transistor between grid and grid spacing indicators home, especially in the forthcoming 10 nano manufacturing technology on the density difference, on the contrary Intel is far ahead, transistor scales spacing done most closely, and scales is higher, thinner, more easy to improve the drive current of transistors and performance.
It is important to note that Intel's 10 nanometers to wait until the end of 2017, while rivals at the end of this year and the beginning of next year. That is to say, Intel's new technology than its competitors late than at least half a year or so. While no one denies the transistor density index is good, the better, but the fact is that Intel has to face in the first half of 2018, TSMC can transition to 7 nano technology process. If we don't know, later means a competitive disadvantage.
Although TSMC said, of course, the 7 nanotechnology will in performance and chip area is better than 10 nanometers, but no mention of designated area under the number of transistors, so whether they narrowed the gap with Intel 10 nanotechnology is unclear. Now to be sure, Intel's "10", "10 +" and "10 + +" will never compromise on the transistor performance.
However, Intel is still the Intel, Intel have power to make any question in the transistor performance advantage competition backward people to shut up, when the samsung and TSMC technology process still can only be used to make mobile chips, Intel has already realized the diversified development, all-powerful can in each market, regardless of whether they are familiar with the server market, or a traditional PC industry, and even the future of the Internet of things devices, Intel seem to do the most good preparation.
