Samsung has already begun to mass produce the 48 layers (or layer within a single NAND 48 units, belongs to the third generation upgrade technology) 3 d V - NAND chips, expects its will be used for SSD T3 (mSATA interface plus 850 EVO V2), NVMe SSD (PM971 - NVMe) and enterprise SSD SSD (PM1633a), and other products. In the midst of all the equipment, will contain a large number of 48 layer 3 d V - NAND memory chips and stack with each other through wire bonding technology. Samsung in 48 layer 3 d V - NAND chip integrated with 512 GB storage unit, means that every NAND chip to 32 GB (256 GB). Samsung's 32 layer (the second generation scheme) 3 d V - 10.67 GB NAND chip (85.33 GB). Therefore, the second and third generation of 3 d V - what is the difference between NAND device? Whether just to upgrade unit layer by 32 to 48?
Researches in this, we have two devices, focusing on unit structure, material, layout, and packaging, etc. See below analysis conclusion:
Storage density and chip plan
As shown in figure 1 to 16 48 layer 3 d V - NAND Chips, MCP) (that is, the more chip packages contain double F - Chips. 48 layers of bare chip obviously higher efficiency. 32 layer 3 d V - NAND chip area is 84.3 square millimeter, and 48 layer 3 d V - 99.8 mm2 NAND chip, means that its length is made up 17.3% solution (as shown in figure 2). Each unit chip storage density up to 2.57 Gb per square millimeter. Now, the top high density 2 d plane NAND device for Toshiba 15 nano TLC NAND, specific level of 1.28 Gb per square millimeter. The biggest difference between them lies in: 1) the plane (NAND storage arrays), 2) a line switch with the page buffer, 3) logic and peripheral area, and 4) to join the F - Chips. Each wafer is divided into two layers. NAND storage array area increased from the original 48.9 mm2 to 68.7 mm2, promoted to 40.3%. While a line switching circuit scheme is consistent with the 32 layer, but the page buffer is narrowed by 20%. Logic and peripheral circuit area is reduced by 34.8%. In other words, samsung has slashed page buffer area and the surrounding area, making it in the storage density and chip efficiency improved. In addition, 16 layer stack in the design of chip thickness also reduced from 132 microns to 36 microns.
Layer 3 d figure a, samsung 48 V - NAND device, using 16 layers vertically stacked NAND chip and double F - Chips, teardown photos.
Figure 2, 32 layer with 48 V - 3 d NAND contrast.
F - Chip
Samsung ISSCC2015 convention in last year's first male announced F - embedded Chip to the NAND flash memory of encapsulation. In general, SSD hardware architecture is Shared by the memory controller, NAND flash memory and DRAM.
F - Chip is responsible for on the I/O bus between the memory controller realize point-to-point topology, and F - Chip will be unnecessary reflection of channel buffer. In addition, the F - Chip in with the NAND device is established between the two sets of internal I/O bus, thus reduce the F - Chip to NAND the load capacity of the interface. In addition, its support to timing model, aimed at the I/O signals from the storage controller to the NAND device.
Again, the F - Chip also improved the NAND device with sequential tolerance in asynchronous interface caused by unstable status regularly. Single - Chip access F eight pieces of V - NAND Chips, means double F - Chips can be embedded to 16 Chip package. As shown in figure 3 is separated from the MCP of F - Chip, containing the ROM, DC power, CMD decoder, data path, the TX/RX and circuit element, such as joint lead plate. F - Chip Chip area is 0.057 square millimeters.
FIG. 3, 48 layer 3 d V - from samsung NAND MCP split of F - in Chip Chip.
Memory cell array structure and architecture
Compared with the second generation of layer 3 d V - NAND, the third generation of layer 3 d V - 48 NAND unit structure has higher unit door number, this means that the process of integration will become more challenges brought about by the requirements and control. Silicon hole with CSL (that is, the common source line) the aspect ratio of the groove etching process is about 33 than 26, above 32 layer 3 d V - NAND device. In addition the high k based on aluminum medium electric barrier layer and the CTF (charge trap flash storage) or CTL (charge trap layer).
Select transistor, including SSL (string selection line) with the GSL (grounding line selection), is proposed to grid design and made plan consistent with the bit line belt, but SEG (silicon epitaxial extension) height to cut. 32 layer 3 d V - NAND device has three metal layers, while 48 layer 3 d V - NAND has four metal layer. Additional a metal layer (commonly known as M0) was added to the CSL/MC level, this may be a unit in order to further improve design efficiency.
Cost considerations: 1 y nano 48 layer 2 d and 3 d V - NAND
For 16 or 15 nano level 1 y MLC/TLC NAND equipment, the process integration in the memory cell array and the surrounding area, including trap/activities/isolation (SA - STI, self aligned STI) form. Unit FG/CG and peripheral door form; And contact and interconnect (metal with a hole) form. , of course, DPT (double pattern technique) or QPT four pattern (technical) design scheme and the air gap process implementation activities, word line and a line of practice are also present in the 2 d plane of NAND products manufacturing process. For 1 y nanometer level 2 d plane NAND equipment, NAND manufacturers often use 40 to 45 mask layer, means that it takes 40 to 45 times lithography steps to integrate equipment on silicon wafers.
32, on the other hand, layer 3 d V - NAND device adopts vertical silicon hole technology (CHT) and 20 nm line half spacing (DPT), means that it needs 50 layer mask to repeatedly adjust the specific design, thus guarantee the storage array peripheral location hole to make the layers of exact connection. Although the storage unit of 48 layer 3 d V - NAND structure/material and unit design, like 32 layer 3 d V - NAND, but in a higher number of gate stack and etching steps will bring throughput, roa and production control problem. As each big mainstream NAND manufacturer actively invest in 48 layer, 64, 64 and even 128 layer 3 d NAND product manufacturing, and continuously improve production believe NAND storage solution using cost will by expanding the scale of the 3 d NAND framework and falling.
NAND flash memory storage technology in the future
Believe that the next few years, 2 d device will work with 3 d NAND parallel exists. However, the process technology of 2 d NAND has been basically reached the limit, and samsung, Toshiba, SanDisk, micron, Intel and SK - hynix mainstream manufacturers began to explore the use of hole mechanism will cause 3-d multi-layer NAND. Once the stackable further increase the number of unit gate, is expected to lead to higher storage density, better performance, better reliability and lower power levels. So far, samsung 32 layer with 48 V - 3 d NAND products with micron/Intel 32 layer 3 d NAND products has been officially put on the commercial market.
Toshiba and SanDisk and SK - hynix 3 d NAND device has not been fully released, means that it into 3 d NAND mainstream manufacturers was on the road a bit slow. Samsung's top 32 layer with 48 V - 3 d NAND flash memory device based on capture charge (CTF) storage architecture (or charge capture layer, CTL), equipped with high k dielectric barrier layer and metal door. CTL belongs to the conductive layer, use the material ACTS as an insulator, such as nitrides and cooperate with other storage cell function in order to reduce the interference between units, so as to control number of errors and improve reliability. Due to the 3 d V - NAND unit is not sensitive to interference between the units, therefore can significantly improve data write speed, resulting in better performance. The number of process steps has been greatly reduced, and power consumption level and therefore get effective control. 48 layer 3 d NAND in the use of 32 layer scheme on the cost curve closer to 2 d flash memory. And may launch in the next few years 64, 96 and even 96 floor layer 3 d NAND may by polysilicon groove mobility, the light etching processing capacity and roa/production control due to the influence of such factors as the capacity is not high.
So now, let's return to the initial question: 48 layer 3 d V - samsung NAND only pure vertical extension of 32 layer scheme? The answer is no. In addition to the vertical extension, a new generation of technology has improved the efficiency of unit performance, embedded F - Chip and the logic and the surrounding area area is reduced by more than 30%, at the same time adding new metal layer to enhance the efficiency of wafer. It is obvious that the 3 d V - NAND has already begun to full maturity.
