Semiconductor manufacturing co (TSMC) held in Austin "Collaborating to Enable the Design with the Latest Processors and FinFET the Processes, o 7 nm" (new technology by the United States, the UK ARM and on June 6, TSMC joint), introduced by 10 nm FinFET and 7 nm FinFET process Design and production progress. The speaker just like last year.

(design and technology platform, deputy director of the)

Use triple exposure for the first time at 10 nm process, the first chips have been sent in the first quarter of 2016 factory (design). Expected to 10 nm process mass production will start in 2016 years. ARM last week (30 May) released by 10 nm process manufacturing aimed at smartphones SoC CPU kernel "ARM Cortex - A73" and GPU kernel "ARM Mali - G71" (see the site reported 2), then announced: equipped with integrated with the kernel of SoC smartphone will be available in 2017.

Consider each layer of different wiring resistance and via resistance design process

As for the 7 nm process, Willy Chen said "have signed more than 20 contract". For users to design, in the second half of 2017 will be sent to factory production. 7 nm process of mass production will begin in 2018. According to Willy Chen, 7 nm process, compared with 10 nm process logic integration will increase by 60%, the performance and power consumption will improve the 30 ~ 40%. In addition, Willy Chen said, hoping to use the technology not only make smartphones, also produce HPC (High Performance Computing) chips.

Although some predict 7 nm process will use four heavy exposure, but it now seems likely as 10 nm process using triple exposure. Willy Chen said "10 nm and 7 nm process design process of the basic same, however, 7 nm process needs to be noted in some places, such as to play a technology of high speed power has three points. Namely: (1) solid clock network method, (2) reduce wiring delays, (3) a more integrated design process.

About (1), neither the traditional clock tree, also don't use the recent high-profile grid structure, and will adopt the method of lie somewhere in between. About (2) the wiring delays, considered separately according to each wiring layer resistance and considered hole resistance is crucial. "According to the length of the wiring to determine the wiring delays have only won't work" (Willy Chen). About (3), you will need to consider each layer of different wiring resistance and via resistance design process.