Future fabs will inevitably downward into testing factory, under the wafer process cannot continue miniature, testing industry will temporarily to system level encapsulation technology will effectively integrate chip do, such as improving chip making profits, provoked beyond Moore's law, the role of moonlight, silicon products and force into active layout.
Taiwan semiconductor association chairman Lou superior, points out that the future is going to do 3 d vertical stack, semiconductor global semiconductor industry toward the kind of Moore's law will be in the future growth.
Wafer miniature will amount to a bottleneck
Ma Guanghua silicon product research and development center, deputy general manager, said the future of the single chip has been unable to continue to shrink, or is said to reduce the cost price has been beyond economic benefits, this time must be through the packaging technology, to promote the performance benefits of the chip, is like a day of moonlight system level (SiP) technology or wafer level packaging, etc.
Ma Guanghua pointed out that the so-called wafer level packaging is the entire wafer directly for assembly and testing, missing parts in the process of packaging materials, production of IC (integrated circuit) is relatively thin, and the fan out of so-called wafer level packaging is also directly on the wafer to fan out packaging, material can be save 3, at the same time chip can be thinner.
Package, future and panel Ma Guanghua explanation, panels package is the direct use of encapsulation, than on the 12-inch wafer cutting IC, can be more efficient and cost saving, wait until the fan out type packaging on the front panel for mature, will appear panel level system level assembly.
The panel package save cost
Now the company is aimed at advanced process packaging, in order to improving the quality of testing, more behind rivals, among them, the moonlight is actively layout type fan out and system level packaging, previously, the moonlight also obtain DECATECHNOLOGIES fan out type wafer level packaging process technology and patent license.
Force into the chairman Cai Dugong said, because the future product development towards a thin and short, but Moore's law after facing limit, it must adopt advanced packaging technology to make up for any deficiencies in this respect, whether it is a 2.5 D, 3 D or type fan out (the Fanout) packaging, etc., into all the devices are ready.
Testing industry, points out that at present both in logic IC or NANDFlash, require 3 d stack technology, can to maximize the benefit exertion of chip, also can achieve the degree of thin and short.
